搜索资源列表
FPGAUART
- 用VHDl设计UART的文章，使用QuartusII平台
apb_uart
- 基于APB总线的UART详细设计方案和实现-APB-based detailed design and implementation of UART
15Altera_IP
- 里面包含15个altera的IP核的源代码,包括I2C，UART，VGA_SYN-Which contains 15 nuclear altera the IP source code, including I2C, UART, VGA_SYN
UART_DESIGN
- The use of hardware descr iption languages (HDLs) is becoming increasingly common for designing and verifying FPGA designs. Behavior level descr iption not only increases design productivity, but also provides unique advantages for design verif
uart
- 异步串行接口设计 vhdl设计 fpga下载模拟-this is a vhdl programm
uart_VHDL
- 基于VHDL的异步串行通信电路uart的设计-VHDL-based asynchronous serial communication circuit design uart
VHDL-PROJECT030609
- parallel communication UART without LCD
uart
- vhdl code source for uart use
FPGA_RS232
- 为增加系统稳定性，减小电路板面积，提出一种基于FPGA的异步串行口IP核设计。该设计使用VHDL硬件描述语言时接收和发送模块在Xilinx ISE环境下设计与仿真。最后在FPGA上嵌入UART IP核实现电路的异步串行通信功能。该IP核具有模块化、兼容性和可配置性，可根据需要实现功能的升级、扩充和裁减。-In order to increase system stability, reduce board space, presents a FPGA-based asynchronous ser
ThedesignofUniversalAsynchronousReceiverTransmitte
- 本课题所设计的UART支持标准的RS．232C传输协议，主要设计有发送模块、接收模块、线路控制与中断仲裁模块、Modem控制模块以及两个独立的数据缓冲区FIFO模块。该模块具有可变的波特率、数据帧长度以及奇偶校验方式，还有多种中断源、中断优先级、较强的抗干扰数据接收能力以及芯片内部自诊断的能力，模块内分开的接收和发送数据缓冲寄存器能实现全双工通信。除此之外最重要的是利用口模块复用技术设计数据缓冲区FIFO，采用两种可选择的数据缓冲模式。这样既可以应用于高速的数据传输环境，也能适合低速的数据传输场
aima
- 基于DMA通过UART发送和接收数据的例子，注意DMA_0为接受通道，DMA_1为发送通道。当然可以将dma的read_master和writer_master同时连在uart_0和sdram_0的从端口上，这样是可以用一个dma对两者读写操作，但是不能同时做双向传输。-Based on DMA send and receive data through the UART example, attention DMA_0 accepted channels, DMA_1 to send the
fifo
- VHDL 带FIFO的 UART 求大神帮忙修改-VHDL with FIFO UART pursuing big God help modify
UART
- UART IN VHDL LANGUAGE IS NOT BEST BUT WORK -UART IN VHDL LANGUAGE IS NOT BEST BUT WORK
UART
- design IP UART by Verilog, VHDL-design IP UART by Verilog, VHDL...
1233
- 基于vhdl的uart设计论文，里面论述清楚，章节明白，具有参考价值-Uart vhdl-based design thesis, which discussed clearly understand chapters, a reference value
fredivn
- UART的异步串口通信协议的VHDL语言实现 异步接收/发送模块-UART asynchronous serial communication protocol of the VHDL language to achieve asynchronous receiver/transmitter module
uart_projet
- uart source code in vhdl also a test bench
Pulse-Generator-Final-Zip
- A VHDL pulse generator that generates customizable square wave pulses on an arbitrary number of channels. Controlled by UART communication through serial port. Tuned for 5ns period clock signal. The pulse width and delay of each channel is fully
uart
- uart_reciver with vhdl (ISE Design Suite 14.7)